1. Field of the Invention
The present invention relates to a semiconductor device.
2. Description of the Background Art
Conventionally, various types of semiconductor devices, an example of which is an IGBT (Insulated Gate Bipolar Transistor), have been proposed.
For example, an insulated gate-type semiconductor device disclosed in Japanese Patent Laying-Open No. 2002-016252 includes a trench gate and a dummy gate disposed on each of opposite sides of the trench gate. Further, the semiconductor device includes a P-type base layer formed between the trench gate and each of the dummy gates, and an emitter electrode formed at a surface of the P-type base layer and at a side surface of the trench gate.
Further, a contact portion is provided on the opposite sides of the trench gate, so that the emitter electrode is brought into ohmic contact with the P-type base layer and an N-type source layer.
It is thereby possible to reduce gate capacitance without decreasing channel density, and alleviate concentration of an avalanche current as well.
Further, an insulated gate-type semiconductor device described in Japanese Patent Laying-Open No. 2001-308327 includes a silicon substrate, an N-type drift layer formed on the silicon substrate and having low impurity concentration, a P-type base region formed on the N-type drift layer and having impurity concentration higher than the impurity concentration of the N-type drift layer, and an n+ source region formed on the P-type base region.
Further, the insulated gate-type semiconductor device includes a groove that penetrates the P-type base region from a surface of the n+ source region and reaches the N-type drift layer, a gate oxide film arranged inside the groove, a gate electrode arranged in the groove with the gate oxide film interposed therebetween, an emitter electrode arranged at surfaces of the P-type base region and the n+ source region, and a collector electrode arranged at the other surface of the silicon substrate.
In this insulated gate-type semiconductor device, a switching loss is reduced while keeping an on-voltage of the trench-type IGBT as low as an on-voltage of an IEGT (Injection Enhanced Gate Transistor), so that the total loss generated therein is reduced.
A semiconductor device described in Japanese Patent Laying-Open No. 2003-188382 includes an n-type base layer, an emitter layer formed under the n-type base layer, a collector electrode formed under the emitter layer, a p-type base layer formed at a surface located on a side opposite to the collector electrode, and an n-type source layer formed at the p-type base layer.
The n-type source layer and the p-type base layer are connected to an emitter electrode. A first trench and a second trench are formed such that they penetrate the p-type base layer from a surface of the n-type source layer and reach an inner portion of the n-type base layer in a depth direction. A gate electrode is formed in the first trench with a gate insulating film interposed therebetween. An embedded electrode is formed in the second trench with an insulating film interposed therebetween. The embedded electrode and the emitter electrode are electrically connected, so that they are at substantially the same potential.
As such, by maintaining the embedded electrode and the emitter electrode at substantially the same potential, a gate voltage is made stable even under a high current, and a nonuniform current, oscillation, and others are suppressed.
A power semiconductor device described in Japanese Patent Laying-Open No. 2004-153112 and Japanese Patent Laying-Open No. 2007-013224 includes a collector layer of a second conductivity type, a first base layer of a first conductivity type formed on the collector layer, and a plurality of trenches disposed apart from one another in the first base layer at positions apart from the collector layer, such that they serve as partitions between a main cell and a dummy cell.
Further, in the power semiconductor device, a second base layer of a second conductivity type and an emitter layer of a first conductivity type are provided in the main cell, while a buffer layer of a second conductivity type is provided in the dummy cell. In a trench adjacent to the main cell, a gate electrode is disposed with a gate insulating film interposed therebetween. A buffer resistor is inserted between the buffer layer and an emitter electrode.
In the power semiconductor device, switching characteristics are improved, while a low on-voltage is maintained.
An insulated gate-type semiconductor device described in Japanese Patent Laying-Open No. 2005-032941 includes a polysilicon film, a gate electrode formed on the polysilicon film and having a trench gate structure, a floating p region formed on the polysilicon film, an insulating film formed on the floating p region, and an emitter electrode which is formed on the insulating film and to which an emitter potential is applied.
The insulating film formed on the floating p region is made thicker than a gate insulating film of the gate electrode, and made thinner than an interlayer insulating film covering the gate electrode. Thereby, a large condenser is formed between the floating p region and the emitter electrode.
The condenser converts the most part of gate-collector capacitance into collector-emitter capacitance and gate-emitter capacitance, so that gate-collector capacitance is effectively reduced.
A semiconductor device described in Japanese Patent Laying-Open No. 2002-353456 includes a P+ substrate, an N+ buffer layer formed on the P+ substrate, an N− layer formed on the N+ buffer layer, and first and second groove portions formed such that they penetrate the N− layer and reach an upper layer portion of the N− layer.
A prescribed number of second grooves are formed between first grooves. The first groove is adjacent to an N+ emitter region, and has a gate electrode formed therein. The second groove has a polysilicon region formed therein. The second groove differs from the first groove in that an N+ emitter region is not formed in its peripheral region, and that it has no gate electrode formed therein.
A trench-to-trench spacing between the first and second grooves adjacent to each other is set to be a distance within a range where a withstand voltage is not lowered. In addition, an emitter electrode is formed directly on approximately the whole surface of the base region. By connecting the emitter electrode as such, operating characteristics are improved while the semiconductor device is being driven.
An insulated gate-type semiconductor element described in Japanese Patent Laying-Open No. 08-316479 includes an n-type drift layer made of low-concentration impurities and formed on a silicon substrate, a p-type base region formed above the n-type drift layer and having concentration higher than that of the n-type drift layer, an n-type carrier storage layer formed immediately below the p-type base region and having concentration higher than that of the n-type drift layer, and an n-type source region formed in the p-type base region. Further, the insulated gate-type semiconductor device includes a groove that penetrates the p-type base region and the n-type carrier storage layer from a surface of the n-type source region and reaches the n-type drift layer, a gate oxide film arranged inside the groove, a gate electrode disposed in the groove with the gate oxide film interposed therebetween, an emitter electrode formed in the p base region and the n-type source region, and a collector electrode formed at the other surface of the silicon substrate.
This structure is called as a carrier storage type IGBT. The n-type carrier storage layer formed under the p-type base region can significantly reduce an on-voltage, so that trade-off is improved.
In some of the semiconductor devices and the power semiconductor device configured as described above, when a voltage between the collector electrode and the emitter electrode is gradually increased, output capacitance (capacitance between the collector electrode and the emitter electrode) and feedback capacitance (capacitance between the collector electrode and the gate electrode) may be decreased drastically.
If output capacitance and feedback capacitance drastically fluctuate as such, an electromagnetic noise tends to be generated, and hence when such a device is mounted and activated, it causes a problem.